Welcome![Sign In][Sign Up]
Location:
Search - pseudo random in vhdl

Search list

[Other resourcepseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2264 | Author: 张庆辉 | Hits:

[VHDL-FPGA-Verilogpseudorandom

Description: 伪随机m序列产生的VHDL语言程序- program in VHDL language for generating pseudo-random m sequence
Platform: | Size: 2048 | Author: 张庆辉 | Hits:

[OtherSC-DSC

Description: 数字通信系统的设计及其性能和所传输的数字信号的统计特性有关。所谓 加扰技术,就是不增加多余度而扰乱信号,改变数字信号的统计特性,使其近 似于白噪声统计特性的一种技术。这种技术的基础是建立在反馈移位寄存器序 列(伪随机序列)理论之上的。解扰是加扰的逆过程,恢复原始的数字信号。 如果数字信号具有周期性,则信号频谱为离散的谱线,由于电路的非线 性,在多路通信系统中,这些谱线对相邻信道的信号造成串扰。而短周期信号 经过扰码器后,周期序列变长,谱线频率变低,产生的非线性分量落入相邻信 道之外,因此干扰减小。 在有些数字通信设备中,从码元“0”和“1”的交变点提取定时信息,若 传输的数字信号中经常出现长的“1”或“0”游程,将影响位同步的建立和保 持。而扰码器输出的周期序列有足够多的“0”、“1”交变点,能够保证同步 定时信号的提取。 -digital communication system design and performance and the transmission of digital signals on the statistical characteristics. The so-called scrambling technology is not to increase the degree to disrupt redundant signal, digital signal change the statistical properties it is similar to white noise statistical characteristics of a technology. This technology is based on feedback shift register sequences (pseudo-random sequence) of the above theory. Decryption is the reverse of the scrambling process, the restoration of the original digital signal. If the digital signal is cyclical, the signal spectrum of discrete lines, as the nonlinear circuit, in multi-channel communication system, these lines of the adjacent channel signal causing crosstalk. And the short-cycle signal after scrambling
Platform: | Size: 113664 | Author: 葛岭泉 | Hits:

[Otherprbs

Description: 伪随机序列产生器,VHDL程序,不记得在哪个论坛上下的。-Pseudo-random sequence generator, VHDL procedures, do not remember in which forum from top to bottom.
Platform: | Size: 2048 | Author: 韩丹 | Hits:

[VHDL-FPGA-Verilogvhdl

Description: 伪随机码发生器的VHDL实现 随着通信理论的发展,早在20世纪40年代,香农就曾指出,在某些情况下,为了实现最有效的通信,应采用具有白噪声的统计特性的信号。另外,为了实现高可靠的保密通信,也希望利用随机噪声。然而,利用随机噪声最大困难是它难以重复产生和处理。直到60年代,伪随机噪声的出现才使这一难题得到解决-Pseudo-random code generator for VHDL realize communication with the development of the theory, as early as the 20th century, 40 years, Shannon has pointed out that in some cases, in order to realize the most effective communications, should be used with the statistical properties of white noise signal . In addition, in order to realize highly reliable secure communication, but also wish to take advantage of random noise. However, the use of random noise the greatest difficulty is that it difficult to repeat the generation and treatment. Until 60 years, the emergence of pseudo-random noise so that this problem only be solved
Platform: | Size: 217088 | Author: 张之晗 | Hits:

[VHDL-FPGA-Verilogfcsr

Description: 伪随机序列产生器-代进位反馈移位寄存器,verilog hdl 原代码。-Pseudo-random sequence generator- on behalf of binary feedback shift register, verilog hdl original code.
Platform: | Size: 1024 | Author: 李辛 | Hits:

[VHDL-FPGA-Verilogpn127

Description: 这是个128位的串行伪随机码发生器,还可以进一步扩充-128 This is a serial pseudo-random code generator, can be further expanded
Platform: | Size: 446464 | Author: lee | Hits:

[VHDL-FPGA-VerilogVHDL

Description: 8*8乘法器设计 伪随机序列发生器 PS2键盘设计 均为VHDL-8* 8 multiplier design of pseudo-random sequence generator are PS2 keyboard design VHDL
Platform: | Size: 2048 | Author: qiumh | Hits:

[source in ebookweisuiji

Description: 伪随机比特发生器, VHdL写的伪随机比特发生器-Pseudo-random bit generator, pseudo-random bit generator, VHdL written in pseudo-random bit generator,
Platform: | Size: 1024 | Author: 阿道夫 | Hits:

[Windows DevelopLFSR

Description: verilog实现的8阶伪随机序列发生器,文件包含了三种主要模块:控制模块,ROM模块,线性反馈移位寄存器(LFSR)模块。已经通过modelsim仿真验证。-verilog to achieve 8-order pseudo-random sequence generator, the file contains three main modules: control module, ROM modules, a linear feedback shift register (LFSR) module. Has passed modelsim simulation.
Platform: | Size: 870400 | Author: 风影 | Hits:

[VHDL-FPGA-VerilogPN7_gen_wtb

Description: 一个用vhdl语言写的产生伪随机数PN7例子,经过altera的fpga测试可以使用。-Written in a language with vhdl generate pseudo-random number PN7 example, after the fpga altera test can be used.
Platform: | Size: 1024 | Author: tofly | Hits:

[VHDL-FPGA-Veriloginterlace

Description: 根据MATLAB中的伪随机交织器产生的交织图案初始化到ROM中,从ROM中读取交织图案对输入数据进行交织。同时也可根据解交织图案进行解交织,同样的算法。-In accordance with MATLAB generated pseudo-random interleaver initialization pattern woven into the ROM, read from the ROM interwoven interwoven pattern of input data. Can also be deinterleaving deinterleaving pattern, the same algorithm.
Platform: | Size: 1024 | Author: 源天 | Hits:

[assembly languageca_prng_latest.tar

Description: Pseudo random noise generator/ implemented in VHDL/Verilog
Platform: | Size: 10240 | Author: ahmed | Hits:

[Communication-Mobilepseudo-sequence-vhdl

Description: 常用的几种伪随机序列的仿真及性能分析,进而运用组合序列的思想,尝试不同的序列以不同组合方式生成的新的伪随机序列,并用FPGA分析其性能,得出组合序列的一般的规律,借此推导出了一种新的组合序列——异族Gold组合序列。-Through simulation and performance analysis of several commonly use¬ d pseudo-random sequence in the FPGA environment, use the ideas of combina¬ tion sequence and try different sequences generated by different combinations ofpseudo-¬ ran¬ d¬ om sequence, and then analyze its performance by using MATLAB. So we get the general laws of combination of sequences to deduce a new combination sequen¬ ce name¬ d interracial Gold combination sequence.
Platform: | Size: 4096 | Author: 杨远望 | Hits:

CodeBus www.codebus.net